1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing an interlayer insulating film in processes in manufacturing a semiconductor device.
2. Description of the Related Art
A multilevel wiring structure is known as one of techniques for increasing the degree of integration of a semiconductor device constituted by an assembly of semiconductor elements such as metal oxide film semiconductor field effect transistors (MOSFET) assembled on a semiconductor substrate. When the multilevel wiring structure is realized by a photolithographic etching method, in order to bury vertical steps of semiconductor elements on a semiconductor substrate and insulate wires from each other, a technique for forming an insulation film layer which is good in planarization is considerably important.
A method of forming an insulating layer having a low-pressure CVD (CVD: Chemical Vapor Deposition) on an insulating film formed on a semiconductor substrate is as follows. For example, tetra-ethoxyorthosilicate (Si(OC2H5)4: to be simply referred to as TEOS hereinafter) is supplied as a source gas into a reaction chamber of a low-pressure CVD in which a semiconductor substrate on which an insulating layer is to be grown is arranged. At this time, an oxygen gas is supplied as an additive gas together with the source gas. A high-frequency voltage is applied across electrodes to generate plasma and to grow SiO2 layer on the semiconductor substrate. In this manner, preferably formation of an insulating layer is realized.
However, since a plurality of wires are arranged on the semiconductor substrate, when an insulating is grown to form an interlayer insulating film as described above method, the insulating film grown on the semiconductor substrate has an uneven portion due to steps of the wires.
In order to remove the uneven portion, the following etch back is executed. That is, a coating film is formed to bury the uneven portion of the insulating film formed on the semiconductor substrate, and the coating film is entirely etched, so that the insulating film formed on the semiconductor substrate is planarized. However, when this process is executed, the following problems are posed. That is, an interlayer insulating film is not easily formed, the steps in manufacturing a semiconductor device is complicated, and manufacturing costs also increases.
In addition, a film forming temperature of an interlayer insulating film in an ultra-large-scale integrated circuit (ULSI) used at the present is 400xc2x0 C. However, in the future, with development of micro patterning of a semiconductor device, a channel of a transistor is further narrowed, and a diffusion layer cannot neglect spreading even though the film forming temperature is 400xc2x0 C.
Furthermore, an organic electro luminescence (to be referred to as an organic EL hereinafter) display, which is considered as a next-generation display with which a liquid crystal display will be replaced, cannot withstand a temperature of more than 100xc2x0 C. at the present. For this reason, the step of forming a film on the organic EL must be performed at a temperature of 100xc2x0 C. or less.
The present invention has been made in consideration of the problems held by a conventional method of manufacturing a semiconductor device, and has as its object to provide a novel and improved method of manufacturing an interlayer insulating film which can manufacture an interlayer insulating film in which recessed portions between wiring grooves formed by causing wires formed on a semiconductor substrate projections to serve as projections are preferably buried with an insulating layer to make it possible to form an insulating layer having excellent planarization property without using an etch-back process.
In order to solve the above problem, according to the viewpoint of the present invention, there is provided a method of manufacturing a semiconductor device including: a step of supplying octa-methylcyclotetrasiloxane as a source gas into a vacuum processing chamber of a vacuum ultraviolet CVD apparatus in which an object on which an interlayer insulating film is to be formed is arranged; and a step of irradiating vacuum ultraviolet light from a vacuum ultraviolet light source arranged on an upper part of the vacuum processing chamber onto the object placed in the vacuum processing chamber to grow an interlayer insulating film.
With this configuration, after a film is formed between wiring grooves at room temperature without using an etch-back process and an oxidizing gas, manufacture of an insulating layer having excellent planarization property and formation of an interlayer insulating film consisting of an SiOCH film having a low dielectric constant are realized.
In addition to the source gas, an inert gas is supplied as an additive gas to regulate the concentration of the source gas, so that the film forming property and film forming rate of the insulating film can be controlled.